The present invention relates to a method for fabricating a metal carbide layer and a method for fabricating a trench capacitor for use in a semiconductor memory cell.
In dynamic random access memory cell configurations, it is virtually exclusively that single-transistor memory cells are used. A single-transistor memory cell contains a read transistor and a storage capacitor. The information is stored in the storage capacitor in the form of an electric charge that represents a logic 0 or a logic 1. Actuating the read transistor via a word line allows the information to be read via a bit line. The storage capacitor must have a minimum capacitance for reliably storing the charge and, at the same time, to make it possible to differentiate the information item that has been read. The lower limit for the capacitance of the storage capacitor is currently considered to be 25 fF.
Since the storage density increases from memory generation to memory generation, the surface area required by the single-transistor memory cell must be reduced from generation to generation. At the same time, the minimum capacitance of the storage capacitor has to be retained.
Up to the 1 Mbit generation, both the read transistor and the storage capacitor were produced as planar components. Beyond the 4 Mbit memory generation, the area taken up by the memory cell was reduced further by using a three-dimensional configuration of the read transistor and storage capacitor. One possibility is for the capacitor to be produced in a trench (see the reference by K. Yamada et al., Proc. Intern. Electronic Devices and Materials IEDM 85, pp. 702 ff.). In this case, a diffusion region which adjoins the wall of the trench and a doped polysilicon filling disposed in the trench act as electrodes for the storage capacitor. Therefore, the electrodes of the storage capacitor are disposed along the surface of the trench. In this way, the effective surface area of the storage capacitor, on which the capacitance is dependent, is increased with respect to the space taken up by the storage capacitor on the surface of the substrate, which corresponds to the cross section of the trench. Although there are limits on the extent to which the depth of the trench can be increased, for technological reasons, the packing density can be further increased by reducing the cross section of the trench.
However, one difficulty of the decreasing trench cross section is the increasing electrical resistance of the trench filling and the associated increase in the read-out time of the DRAM memory cell. Therefore, to ensure a high read-out speed as the trench cross section is further reduced in size, it is necessary to select materials with a lower resistivity for the electrodes of the trench capacitor. In current trench capacitors, the trench filling consists of doped polycrystalline silicon, so that as miniaturization continues a high series resistance of the trench filling results.
There have already been various proposals for depositing a metal or a layer sequence which contains a metal-containing layer onto the storage dielectric in the trench. A general problem in this context is the high aspect ratio of the capacitor trench into which a layer sequence has to be deposited if possible in such a manner that it forms a good and permanent mechanical and electrical contact with the storage dielectric below it and that no voids are formed within the capacitor electrode. A further problem is that many metals do not have a particularly high ability to withstand heat.
Published, European Patent Application EP 0 981 158 A2 describes the fabrication of a DRAM memory cell which has a trench capacitor and a select transistor which is connected thereto via a buried strap. The trench capacitor has a lower capacitor electrode, which adjoins a wall of the trench, a capacitor dielectric and an upper capacitor electrode. The trench capacitor is fabricated by forming the upper capacitor electrode in the lower trench region, then depositing an insulating collar in the upper trench region, and then completing the upper capacitor electrode. With regard to the trench filling which forms the upper capacitor electrode, it is specifically stated that this filling may be formed by a metal both in the lower region of the trench and in the upper region of the insulating collar. In any event, however, the trench filling in the region of the insulating collar is formed in one step and therefore from the same material as the buried strap. Therefore, if a metal is formed into the insulating collar, the buried strap also has to be formed from metal. However, in this context it is possible that the select transistor may be adversely affected by the contact that is made with a highly conductive material at the drain region. Moreover, no details are given as to the nature of the metal that is to be used.
U.S. Pat. No. 5,905,279 discloses a memory cell having a storage capacitor disposed in a trench and a select transistor. The storage capacitor has a lower capacitor electrode, which adjoins a wall of the trench, a capacitor dielectric and an upper capacitor electrode. The upper capacitor electrode contains a layer stack formed of polysilicon, a metal-containing, electrically conductive layer, in particular made from WSi, TiSi, W, Ti or TiN, and polysilicon. The trench capacitor is fabricated by first forming the upper capacitor electrode in the lower trench region. Then, an insulating collar is deposited in the upper trench region, and next the upper capacitor electrode is completed. Alternatively, the method is carried out on a silicon-on-insulator (SOI) substrate which does not have an insulating collar, in which case the upper capacitor electrode, which contains a lower polysilicon layer and a tungsten silicide filling, is fabricated in a single-step deposition method, in which the individual layers are deposited entirely in the trench. Although the metals described in this document, such as tungsten, titanium or silicides thereof, are highly temperature stable, the reduction in the series resistance of the upper capacitor electrode which can be achieved in theory with this method is still unsatisfactory.
International Patent Disclosure WO 01/29280 discloses a method for depositing thin layers of metal carbide by an alternating deposition of a transition metal layer and a carbon layer with layer thicknesses at the atomic level (atomic layer deposition (ALD)) on a substrate. Rearrangement processes on the heated substrate result in the formation of a metal carbide layer in situ.
U.S. Pat. No. 5,680,292 likewise describes, inter alia, a method for forming tungsten or molybdenum carbide layers. First, a corresponding metal oxide layer is deposited, and then the layer is subjected to a carbon treatment at elevated temperature in an oxygen-reducing environment.
It is accordingly an object of the invention to provide a method for fabricating a metal carbide layer and a method for fabricating a trench capacitor containing a metal carbide which overcomes the above-mentioned disadvantages of the prior art methods of this general type, which makes it possible to form the trench capacitor with a reduced series resistance and a high thermal stability. A second object of the present invention is to provide a method for fabricating a metal carbide layer that is able to simplify the shaping or patterning of the metal carbide layer.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a trench capacitor for use in a semiconductor memory cell. The method includes the steps of providing a substrate, forming a trench in the substrate, forming a lower capacitor electrode adjoining a wall of the trench in a lower trench region, and providing a storage dielectric. In the trench, the storage dielectric adjoins the lower capacitor electrode. An upper capacitor electrode is provided and is formed as a trench filling and adjoins the storage dielectric. The upper capacitor electrode is at least partly formed by metal carbide.
A first aspect of the present invention is based on the idea of fabricating the trench filling, which forms the upper capacitor electrode, of the trench capacitor at least in part from metal carbide.
In particular, the carbides of the transition metals from subgroups IV, V and VI of the periodic system, i.e. in particular the metals Mo, W, Ta, Ti, Zr, Hf, V, Nb, have a number of advantages which make them suitable for the upper capacitor electrode of the trench capacitor of a semiconductor memory cell. In addition to their mechanical hardness and chemical stability, they are also distinguished by a high thermal stability (melting point greater than 2500xc2x0 C.) and high electrical conductivity (resistivity less than 70 xcexcxcexa9xc2x7cm). Particularly the latter two properties are generally of considerable interest for use as electrode materials in semiconductor fabrication technology.
The trench filling may be formed completely or only partially by the metal carbide. Therefore, before and/or after the formation of the metal carbide section of the trench filling, it is additionally possible to deposit other conductive materials, such as polycrystalline silicon or other metal-containing materials, in the trench.
The metal carbide can be deposited directly in the trench by a chemical vapor deposition (CVD) process, for example, in the case of tungsten carbide, by using a WF6/C3H8/H2 mixture (in a ratio of 1:15:16) at a temperature of 1170 K in the CVD reactor. However, patterning of the electrodes causes problems in the fabrication of electrodes from homogeneous metal carbide material. The chemical stability of the substances results in that a high proportion of the dry etching processes which may be considered results from the physical component. However, as a result, the etching rate of the carbide layers is of the same order of magnitude as the etching rate of the mask used for the etching. Furthermore, there may be high levels of redeposition on the mask, the substrate or on the installation itself.
Therefore, a second aspect of the present invention relates in general terms to a method for fabricating a metal carbide layer, in which, in a first method step of the fabrication, an alternating sequence of at least one metal-containing layer and at least one carbon-containing layer is deposited on a substrate and, in a subsequent, second method step, a heat treatment step is carried out in such a manner that the layer sequence is intimately mixed and converted into a substantially homogeneous metal carbide layer. The substrate may in this case be the dielectric of a capacitor, for example of a trench capacitor.
The deposition of the metal-containing and carbon-containing layers may be carried out by conventional chemical vapor deposition (CVD) processes. The method according to the invention relates in particular to the situation in which the metal-containing and carbon-containing layers are each formed from an elemental metal, such as tungsten (W), and from carbon (C) respectively. The layers of the alternating sequence are deposed until the trench is filled.
The method in accordance with the second aspect allows relatively simple patterning of the metal carbide layer as a result of the patterning being carried out by etching or the like before the metal carbide layer is formed, i.e. before the heat treatment step. This therefore makes it possible to use etching methods by which the metal-containing layer and the carbon-containing layer can be etched individually. Since the layers are generally easier to etch than the completed metal carbide layer, in practice the method is easier to carry out.
It is merely necessary to ensure that the etching rates of the metal-containing layer and of the carbon-containing layer should be substantially identical. In particular, the ratio of the etching rates of the metal-containing layer to the carbon-containing layer should lie in the range between 0.7 and 1.3. Examples of suitable etching media are NF3 or SF6 or mixtures thereof.
The heat treatment step may be carried out in a non-oxidizing protective gas atmosphere, with argon or mixtures of argon and hydrogen being particularly suitable protective gases. It is particularly advantageous if a hydrocarbon, in particular a simple hydrocarbon, such as for example propane, is added to the protective gas in order to prevent carbon from diffusing out of the layers, forming volatile hydrocarbons in the H2 atmosphere. A hydrocarbon level of 1% is sufficient for this purpose.
The heat treatment is preferably carried out at temperatures in a range between 600xc2x0 and 1200xc2x0 C. In rapid thermal process (RTP) installations, the treatment times are between 30 and 120 seconds, and in conventional furnace processes the treatment times are between 15 minutes and 2 hours.
Furthermore, it is possible that a metal carbide layer is to be formed with a desired stoichiometric ratio between the metal and the carbon, for example in the form of WC, W2C, W3C or WC1xe2x88x92x. In this case, the metal-containing layers and the carbon-containing layers are deposited in a thickness or quantitative ratio with respect to one another which is such that, after the intimate mixing, the desired stoichiometric composition of the metal carbide layer which is to be formed results.
The method for fabricating a metal carbide layer in accordance with the second aspect represents a preferred embodiment for carrying out the method according to the invention for fabricating a trench capacitor, not least on account of the simplified patterning. This is because, in a method of this type, it is generally necessary to carry out at least one patterning or etching step, by which the trench filling of the upper capacitor electrode, after it has been deposited, is etched back again in part, i.e. to below the surface of the semiconductor substrate. In view of the high aspect ratios, in this context it is advantageous if the etching step does not encounter any major problems and can substantially be carried out in a conventional manner using a conventional etching medium.
In accordance with an added mode of the invention, there is the step of depositing a polycrystalline, doped silicon layer on the storage dielectric as part of the upper capacitor electrode.
Embodiments of the fabrication of a trench capacitor for a semiconductor memory cell are explained in more detail below. In the variants, in each case at least part of the upper capacitor electrode is formed by a metal carbide layer.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for fabricating a metal carbide layer and a method for fabricating a trench capacitor containing a metal carbide, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.